Embodiments of the disclosed technology relate to an array substrate, a manufacturing method for an array substrate, and a liquid crystal display (LCD).
LCDs have become common in applications, and especially TFT-LCDs (Thin Film Transistor Liquid Crystal Displays) have been prevailing in the market.
An array substrate is an important component of a LCD. The array substrate can be manufactured through a set of patterning processes each comprising thin film deposition steps and photolithograph steps with one photolithograph step for one layer of pattern. Generally, one patterning process comprises: depositing a thin film on a base substrate, applying a layer of photoresist on the surface of the thin film, forming a photoresist pattern with a mask plate having the pattern to be formed, then etching the underlying thin film to transfer the pattern to the thin film. Each layer of pattern should be precisely laid on another layer of pattern, and the materials of the pattern layers may be the same or not with thickness from hundreds nanometers to several micrometers.
The existing array substrates are typically manufactured through a four-mask process, which comprises: forming gate electrodes and gate lines on a base substrate in the first patterning process; forming patterns comprising data lines, active layers, source and drain electrodes in the second patterning process with a double-tone mask plate such as a half tone mask plate or a grey tone mask plate; forming a passivation pattern including passivation via holes in the third patterning process; and forming a pattern comprising pixel electrodes in the fourth patterning process.
FIG. 1A shows a partial structural schematic top view of an existing typical array substrate; FIG. 1B shows a structural schematic sectional view taken along with line A-A in FIG. 1A. As shown in FIG. 1A and FIG. 1B, the array substrate manufactured with the existing four-mask process comprises: a base substrate 1, data lines 5 and gate lines 2 that intersect with each other on the base substrate 1, and pixel units in a matrix array that are defined by the data lines 5 and gate lines 2; each pixel unit comprises a thin film transistor (TFT) switch element T and a pixel electrode 11. The TFT switch element T comprises a gate electrode 3, a source electrode 7, a drain electrode 8 and an active layer 6; the gate electrode 3 is connected with a gate line 2, the source electrode 7 is connected with a data line 5, and the drain electrode 8 is connected with the pixel electrode 11 through a passivation layer via hole 10 in a passivation layer 9; the active layer 6 is formed between the layer of the source electrode 7 and the drain electrode 8 and the layer of the gate electrode 3, a gate insulating layer 4 is formed between the gate electrode 3 and the active layer 6, and the passivation layer 9 is formed between the pixel electrode 11 and the drain electrode 8. The patterns of the gate lines 2, the data lines 5, the gate electrodes 3, the source electrodes 7, the drain electrodes 8, the pixel electrodes 11, and so on can be collectively referred to as conductive layer patterns, while the patterns of the gate insulating layer 4 and the passivation layer 9 can be collectively referred to as insulation layer patterns.
In the pixel unit structure of the array substrate formed by the existing four-mask process, the source electrode 7 and the drain electrode 8 are overlapped in part with the gate electrode 3, forming a parasitic capacitor Cgs therebetween, and the value of the parasitic capacitance is related to the overlapping area between the gate electrode 3 and the source electrode 7 or the drain electrode 8. Because the gate electrodes formed in the existing process typically have a relatively big thickness of, e.g., 3000˜6000 Å, the gate electrodes at different positions on the base substrate have different grade angles, which cannot be formed identically in a precise way, along their sides, and this results in different overlapping areas between the drain electrodes or the source electrodes and the gate electrodes and further makes parasitic capacitance in different pixel units over the entire array substrate different from one another to a great degree.
In addition, the relationship between the value of the parasitic capacitance and the kickback voltage ΔVp can be expressed in the following equation (1):
                              Δ          ⁢                                          ⁢                      V            p                          =                              (                                          V                gh                            -                              V                gl                                      )                    ⁢                                          ⁢                                    C              gs                                                      C                gs                            +                              C                lc                            +                              C                s                                                                        (        1        )            
where ΔVp is referred to as “kickback voltage,” Vgh is a high level transmitted over the gate line, Vgl is a low level transmitted over the gate line, Cgs is parasitic capacitance, Cs is storage capacitance, and Clc is liquid crystal capacitance. It can be known from the equation (1) that ΔVp varies with the change of the parasitic capacitance Cgs, which makes non-uniform the ΔVp over the entire array substrate, and this non-uniformity is difficult to be compensated with a driving circuit.
From the above, it can be seen that different pixel units over the array substrate have parasitic capacitance different from one another to a relatively great degree, and during the operation of the array substrate, it is difficult to adjust ΔVp on the overall array substrate, resulting in flickering of the displayed images and degraded display quality of the LCD.